The present invention relates to computer memory systems, and more specifically, to lateral cast out of cache memory of a processor in a computer system.
In some computer systems, cache memory can increase instruction and data processing throughput, but cache memory can be difficult to test. Validation and verification processes during cache memory system development can apply traffic to cache memory to confirm that the cache memory is operating as expected. Cache memory may be readily accessible to test equipment during early stages of cache memory system development. However, when the cache memory is incorporated within a device, such as a processor, verification and validation become more challenging in a post-silicon phase of processor development.